1. Field of the invention
The present invention relates to an analog/digital converter, more particularly to an analog/digital converter capable of converting analog voltages to digital values with a high accuracy at a high speed.
2. Description of Related Art
FIG. 1 is a schematic diagram illustrative of an analog/digital converter of the prior art. Analog voltages A.sub.IN0 through A.sub.INi to be converted to digital values are input to an input control circuit 100. Analog voltages output from the input control circuit 100 are input to a switching circuit 101. A reference voltage output from a selector circuit 9 which selects the reference voltage generated by a ladder resistor 10 is input to the switching circuit 101.
The analog voltage and the reference voltage which are output from the switching circuit 101 are input to a comparator 4, while the comparison output signal from the comparator 4 is input to a latch circuit. 103. Latched data of the latch circuit 103 is input to a sequential comparison register 7, while data stored in the sequential comparison register 7 is input to a decoder circuit 8. Decoded signal output from the decoder circuit 8 is sent to the selector circuit 9. A control circuit 108 is also provided to generate a timing signal for the control of various circuits.
FIG. 2 is a block diagram illustrative of the constitution of the analog/digital converter shown in FIG. 1. The switching circuit 101 has transmission gates 2, 3. An analog voltage A.sub.IN which is input to an external analog input terminal 1 is sent to the comparator 4 via the transmission gate 2. The reference voltage V.sub.REF is output from the selector circuit 9 which selects the reference voltage generated by the ladder resistor 10 and is input to the comparator 4 via the transmission gate 3. The comparison output signal from the comparator 4 is input to the latch circuit 6 via a transmission gate 5.
The latch circuit 103 has the transmission gate 5 and the latch circuit 6. Data latched in the latch circuit 6 is input to the sequential comparison register 7, while data stored therein is input to the decoder circuit 8. Decoded signal output from the decoder circuit 8 is sent to the selector circuit 9. The transmission gates 2, 3 receive switching signals TS, #TS at the gates thereof. The comparator 4 receives a comparison control signal TZ. The transmission gate 5 receives a latch signal TL at the gate thereof. The input control circuit 100 and the control circuit 108 are not shown in the drawing.
FIG. 3 is a block diagram illustrative of the constitution of the comparator 4. The comparator 4 comprises a capacitor 30, an inverter 31, a capacitor 33, an inverter 34, a serial circuit of an inverter 36 and an inverter 37 of negative logic for the input, a transmission gate 32 connected in parallel with the inverter 31 and a transmission gate 35 connected in parallel with the inverter 34.
The capacitor 30, the inverter 31 and the transmission gate 32 constitute a chopper amplifier, while the capacitor 33, the inverter 34 and the transmission gate 35 constitute another chopper amplifier. The transmission gates 32, 35 receive the comparison control signal TZ at the gates thereof.
FIG. 4 is a block diagram illustrative of the constitution of the latch circuit 6. The latch circuit 6 comprises a serial circuit of an inverter 38 connected to the transmission gate 5 and an inverter 39 of negative logic for the input, a transmission gate 40 connected in parallel with the serial circuit of the inverters 38 and 39, and a NOR circuit 41 with the output thereof being connected to the gate of the transmission gate 40. The NOR circuit 41 receives latch signals TL, TL at the input terminals thereof.
Now the operation of the chopper amplifier will be described below with reference to FIG. 5 which shows the input-output characteristic of the inverter. In case the inverters 31, 34 are constituted from CMOS gates, input-output characteristic of the inverters 31, 34 becomes as shown by solid line in FIG. 5. When the comparison control signal TZ turns to H level so that the transmission gate 32 conducts, one of the chopper amplifiers is biased to point A.
When potential difference .DELTA. V of the input voltage V.sub.IN of the capacitor 30 changes to a positive value (.DELTA. V&gt;0) after the comparison control signal TZ turns to L level under the biased condition as described above so that the transmission gate 32 does not conduct, output voltage V.sub.OUT of the chopper amplifier shifts from point A to point B. When potential difference .DELTA. V of the input voltage V.sub.IN changes to a negative value (.DELTA. V&lt;0), output voltage V.sub.OUT of the chopper amplifier shifts from point A to point C. In such a sequence, the chopper amplifier compares the magnitudes of two input voltages V.sub.IN.
Now the operation of the analog/digital converter will be described below with reference to FIG. 6 which shows the timing charts of signals. When the switching signal TS turns to H level during a period .phi..sub.1, the transmission gate 2 conducts so that the analog voltage A.sub.IN which is inputted to the external analog input terminal 1 is sent to the comparator 4. When the comparison control signal TZ turns to H level, the transmission gates 32, 35 conduct so that the chopper amplifier of the comparator 4 is put in setup state, namely in such a state as the point of operation is biased to the point A shown in FIG. 5.
Then when the switching signal TS turns to L level during a period .phi..sub.2, the transmission gate 2 is put in non-conducting state. Also the switching signal #TS turns to H level so that the transmission gate 3 conducts and the reference voltage V.sub.REF is input to the comparator 4. Output of the comparator 4 is determined as follows depending on the value of the deviation of the input voltage .DELTA. V=A.sub.IN -V.sub.REF of the comparator 4. EQU A.sub.IN &gt;V.sub.REF : Output of comparator="1" (1) EQU A.sub.IN &lt;V.sub.REF : Output of comparator="0" (2)
The reference voltage V.sub.REF is a voltage divided into a plurality of parts by the ladder resistor 10. One reference voltage V.sub.REF is selected by the selector circuit 9 according to the decoded signal from the decoder circuit 8 and is output. The decoder circuit 8 decodes the data stored in the sequential comparison register 7.
In case the sequential comparison register 7 is made to have 10-bit capacity, the most significant bit b.sub.9 is automatically set to "1" before the start of analog to digital conversion, so that it becomes (b.sub.9, b.sub.8, b.sub.7, b.sub.6, b.sub.5, b.sub.4, b.sub.3, b.sub.2, b.sub.1, b.sub.0)=(1, 0, 0, 0, 0, 0, 0, 0, 0, 0).
In the case of A.sub.IN &lt;V.sub.REF, output of the comparator 4 becomes "0", the latch circuit 6 latches a value "0" at the time of t.sub.1 by the latch signal TL. This operation of comparison determines the value of the most significant bit b.sub.9.
Then at the time t.sub.2 during a period .phi..sub.3, value "0" is set at bit b.sub.9 of the sequential comparison register 7 according to the data latched in the latch circuit 6, while value "1" is automatically set to bit b.sub.8. Thus the bit pattern of the sequential comparison register 7 becomes (b.sub.9, b.sub.8, b.sub.7, b.sub.6, b.sub.5, b.sub.4, b.sub.3, b.sub.2, b.sub.1, b.sub.0)=(0, 1, 0, 0, 0, 0, 0, 0, 0, 0).
Because the switching signal TS turns to H level, the input analog voltage A.sub.IN is input to the comparator 4, to put the chopper amplifier in setup state. Further during a period .phi..sub.4, the switching signal TS turns to L level and the switching signal #TS turns to H level so that the transmission gate 2 becomes non-conducting, then the transmission gate 3 conducts so that the reference voltage V.sub.REF selected according to the data stored in the sequential comparison register 7 and the input analog voltage A.sub.IN are compared.
In the case of A.sub.IN &gt;V.sub.REF, output of the comparator 4 becomes "1" and is latched by the latch circuit 6 at the time t.sub.3 according to the latch signal TL. This operation of comparison determines the bit b.sub.8. Such operations are repeated to determine the bits b.sub.9 through b.sub.0 to complete the operation of analog to digital conversion of the 10-bit data.
When reading out the result of analog to digital conversion to the outside, a data bus not shown in the drawing is connected to the sequential comparison register 7 and the result of analog to digital conversion is read out. Timing signals such as the switching signals TS, #TS, the comparison control signal TZ and the latch signal TL are generated by the control circuit 108 (refer to FIG. 1).
In the analog/digital converter of the prior art, however, increasing the speed of analog to digital conversion decreases the length of period during which the chopper amplifier of the comparator is put in setup state, thereby making the point of operation of the chopper amplifier unstable, resulting in a problem of decreasing accuracy of analog/digital conversion. Also there is a problem that two analog voltages cannot be converted to digital data at a high speed.